Efficiency and flexibility are important tools in the hands of signal processing engineers who design the latest generation wireless communication handsets. Each dollar saved by reducing silicon area and maximizing design reuse is a dollar that can be applied to profit and the manufacturer's bottom line. In that regard, simplifying design interfaces and minimizing interaction between electronic components results in cost savings such as reduced silicon area, power requirements, and design time.
One area where such cost savings can be realized is in the design of signal processing pipelines. A primary function of signal processing pipelines is to change data rates as the data is being conveyed through the pipeline. For example, in certain rate-changing filter pipelines, the incoming data is down-converted and interpolated. When pipeline interpolation is performed, a conventional technique used to prevent a downstream element from being overwhelmed by increased data rates is to buffer the data in the pipeline with a memory interface device. A typical memory interface device used to buffer data in a signal processing pipeline is a First-In First-Out (FIFO) memory device, which allows each element in the pipeline to source or accept data at its own rate. An example of a conventional interpolation signal processing pipeline with such a FIFO buffer device is shown in FIG. 1.
FIG. 1 depicts a simplified block diagram of a conventional interpolating filter signal processing pipeline 100, which illustrates the use of a FIFO memory element as a buffer device. Referring to FIG. 1, pipeline 100 includes an interpolating element 102, a memory (FIFO) storage element 104, and a receiving element 106. Note that a first clock line 108a is provided to clock incoming data into the memory element 104 at a rate compatible with that of the interpolating element 102, and a second clock line 108b is provided to clock data out of the memory element 104 at a rate compatible with that of the receiving element 106.
The disadvantages of existing signal processing pipelines are known. For example, the memory elements (e.g., FIFOs) typically used as buffers consume a substantial amount of silicon for the control logic and storage circuitry involved. In this regard, a relatively complex control interface is needed to enable both pipeline elements 102 and 106 to access the memory storage array (104). For systems with multiple data rates (e.g., each data rate associated with a different communication protocol), the memory element in the pipeline has to be sized in such a way that it can handle the largest predicted data influx. However, if a new pipeline design is envisioned with different technical requirements, the memory element typically has to be redesigned. Consequently, in that case, the entire signal processing pipeline circuit has to be redesigned. The increased development costs incurred as a result of such a redesign are disadvantageous particularly for cost sensitive applications.